Lead Product Engineer
At a glance
Senior Software Engineering role at Cadence. San Jose · full-time · $119,000–$221,000 base.
techroles summary, based on the employer's posting.
What you'll do
- Carry CPU or GPU designs from RTL through signoff, covering block and full-chip implementation
- Close timing and improve power and area through physical design analysis and optimization
- Apply low-power methods such as power gating, multi-voltage designs and clock gating
- Build scripts and implementation methods that improve productivity and design quality
- Debug complex design issues and work with architecture, RTL, verification, methodology and CAD teams
What you bring
- Hands-on experience implementing high-performance, power-critical CPU or GPU designs from RTL to signoff
- Strong command of physical design, timing closure, power analysis and low-power implementation approaches
- Ability to develop automation scripts and utilities; experience with Python, Tcl, Perl or Shell is a plus
- Familiarity with industry-standard implementation and signoff tools
Who this fits
This senior engineering role suits someone focused on CPU or GPU implementation, timing closure and power optimization. The position is based in San Jose, California.
From the employer
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
High-performance and Power-Critical CPU and/or GPU Implementation and Methodology Engineer
Responsibilities / Skills
· Full-chip and block-level implementation from RTL to Signoff, including place-and-route, timing closure, physical verification, power analysis, and optimization.
- Strong understanding of physical design fundamentals including floorplanning, placement, clock tree synthesis, routing, timing analysis, signal integrity, IR drop, and electromigration.
- Experience with timing closure methodologies for setup, hold, power, and area optimization.
- Familiarity with low-power implementation techniques including UPF/CPF, power gating, multi-voltage designs, clock gating, and leakage optimization.
- Need to be automation savvy and able to develop scripts, utilities, and methodologies to improve productivity and design quality.
- Prior experience in Python, Tcl, Perl, Shell, or other programming/scripting languages is a plus.
- Exposure to machine learning and AI-assisted optimization techniques is a plus.
- Familiarity with industry-standard implementation and signoff tools
- Understanding of advanced technology nodes (5nm and below) and associated challenges including congestion, variability, power integrity, and manufacturability is desirable.
- Strong debugging and problem-solving skills with the ability to analyze complex design issues and drive them to resolution.
- Good communication skills and ability to work effectively with cross-functional teams including architecture, RTL, verification, methodology, and CAD teams.
- Experience with data analytics, design-space exploration, or AI-driven optimization frameworks for improving PPA and productivity is highly desirable.
- Experience in PPA optimization, design convergence, benchmarking, methodology development, and large-scale CPU/GPU implementation is a plus.
The annual salary range for California is $119,000 to $221,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.