Lead Functional Product Engineer, Power Analysis
Cadence Open · verified Oct 24, 2026 At a glance
Senior Software Engineering role at Cadence. San Jose · full-time · $114,800–$213,200 base.
techroles summary, based on the employer's posting.
What you'll do
- Build and maintain signoff power-analysis flows with R&D, connecting them to synthesis and place-and-route stages
- Recreate customer issues in power tools and flows, then diagnose and fix their causes
- Install and verify power-analysis tools at customer sites, providing practical technical assistance
- Work with customers to improve power results and make analysis flows run more efficiently
- Automate repeatable flow deployments and record debugging lessons and operating guidance
What you bring
- At least three years of industry experience
- A B.E./B.Tech, M.E./M.Tech or equivalent in electronics, VLSI, computer engineering or a related field
- Hands-on work with static and dynamic signoff power analysis, plus understanding of UPF and low-power design methods
- Verilog or SystemVerilog skills, scripting in Tcl, Python or Shell, and familiarity with Liberty and SPEF formats
Who this fits
This senior engineering role suits someone who can work directly on power-analysis flows and troubleshoot with customers. The position is based in San Jose, and customer-site deployment and support are part of the work.
From the employer
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
We are looking for a skilled engineer to join our Power Analysis team, focused on developing, debugging, and deploying Signoff power analysis flows at customer environments.
Key Responsibilities
- Closely work with R&D to develop and maintain Signoff power analysis flows including integration with synthesis and PnR stages
- Reproduce, debug, and resolve customer-reported issues in power analysis tools and flows
- Deploy and validate power analysis tools at customer sites; provide hands-on technical support
- Collaborate with customers to optimize power results and improve flow efficiency
- Contribute to flow automation and scripting for repeatable deployments
- Document debug findings, best practices, and flow guidelines
Required Skills
- Hands-on experience with Signoff power analysis (static and dynamic power)
- Knowledge of power optimization techniques in Synthesis (clock gating, operand isolation, multi-Vt cell selection,
- Working knowledge of UPF (Unified Power Format) — power domains, isolation, level shifting, retention
- Proficiency in Verilog/SystemVerilog for design analysis and testcase creation
- Understanding of digital design fundamentals — clock domains, pipeline stages, timing/power trade-offs
- Experience with low-power design methodologies (DVFS, power gating, multi-voltage)
- Familiarity with Liberty (.lib) and SPEF formats
- Scripting skills: Tcl, Python, or Shell
- Familiarity with tools such as Joules, Voltus, PTPX or equivalent
Education & Experience
- B.E./B.Tech or M.E./M.Tech in Electronics / VLSI / Computer Engineering or equivalent
- Must have 3+ years of industry work experience
The annual salary range for California is $114,800 to $213,200. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
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