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Technical Staff Engineer - Design

Microchip Open · verified Oct 24, 2026
Burnaby Full-time Senior Engineering Leadership

At a glance

Senior Engineering Leadership role at Microchip. Burnaby · full-time · CA$107,000–CA$226,000 base.

SalaryStated by Microchip
CA$107,000 – CA$226,000
Base salary for this role, in CAD per year, as published in the posting.
This role, from MicrochipOur estimate for the market: CA$136,000–CA$238,500Median CA$173,750
The range includes the market median of CA$173,750 for senior engineering leadership roles in Burnaby.
Worked out from 6 postings that stated pay, median CA$173,750. Last updated Sep 30, 2026.
RoleEngineering Leadership
SenioritySenior
LocationBurnaby
EmploymentFull-time
Base payCA$107,000–CA$226,000
PostedAug 14, 2026 · 2mo ago
Role brief

techroles summary, based on the employer's posting.

What you'll do

  • Plan pad rings and bump layouts, accounting for package needs and system-level limits
  • Build and update IO connections, pad ring definitions and bump patterns through the design cycle
  • Prepare and check handoff files, including pad ring DEFs, Verilog netlists and bump maps
  • Coordinate IO and package requirements with architecture, design, packaging, implementation and foundry teams
  • Investigate IO issues with verification, emulation, silicon validation and debug teams, then improve the design

What you bring

  • A bachelor’s degree in electrical engineering and at least twelve years of related experience
  • Hands-on work planning pad rings, placing IO cells and defining bump layouts for advanced SoCs
  • Knowledge of IO library cells, IO standards and interfaces such as SerDes, DDR, PCIe or CXL
  • Experience producing IO handoff data, familiarity with RTL, LEF and Liberty views, and scripting in Tcl or Python

Who this fits

This senior design role suits an experienced engineer who can take controller SoC design work from planning through production and coordinate across multiple technical teams. Travel may range from zero to twenty-five percent.

From the employer

Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.

People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.

Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.

Visit our careers page to see what exciting opportunities and company perks await!

Job Description:

The successful candidate will join the rapidly growing Data Center Solutions (DCS) business unit at Microchip. DCS has a broad portfolio of products widely deployed by the industry’s cutting-edge server/storage OEMs and hyperscale datacenters. Customers deploy DCS solutions into applications ranging from Big Data capacity storage to artificial intelligence and machine learning that are helping to shape the next digital age. Our product portfolio includes SAS/PCIe/NVMe/CXL products that connect, manage, and secure the world’s information, including Flash Controllers, High Performance Switches, RAID Controllers and Memory Controllers. Join a team where you can expand your skill set and drive key elements of the industry’s technology leadership.

An opening exists for Tech Staff Design Engineer with an interest in developing the next generation of storage and memory controller SoC products. This will involve taking a design from initial concept through to production. Throughout you will work beside experienced engineers and be exposed to Microchip’s Best-In-Class engineering practices. Working side-by-side with some of the brightest minds and most innovative people in the industry, you won't just fill a position, you will be given an opportunity to work on a team where your contributions matter. Microchip fosters continuous learning in a challenging and rewarding environment. If this sounds like the kind of environment you'd like to participate in, we'd like to hear from you!

As a Staff Design Engineer, your job will entail the following:

  • Own design planning and construction of pad rings, bump patterns, ensuring alignment with package and system-level constraints.

  • Develop, implement, and maintain IO connectivity, pad ring definitions, and bump pattern designs throughout the design cycle.

  • Generate and validate physical design handoff deliverables including pad ring DEF files, Verilog netlists, bump maps, and associated implementation data for downstream teams.

  • Ensure IO and pad ring designs comply with design standards, package constraints, and implementation best practices.

  • Collaborate with Architecture, Product Design, Internal IP Packaging, Implementation, Product Engineering, Technology Development, and Foundry teams to align on IO/package requirements and resolve technical issues.

  • Support Verification, Emulation, ASIC validation, and silicon debug efforts by analyzing IO-related issues and driving design improvements.

Requirements/Qualifications:

  • B.S degree in electrical engineering with 12+ years related experience.

  • Hands-on experience with pad ring planning, IO cell placement, and bump map/pattern definition for advanced SoC designs.

  • Knowledge of IO library cells, IO standards, and PHY-level IO interfaces (SerDes, DDR, PCIe, CXL).

  • Experience with IO planning and implementation EDA tools (e.g., Orbit IO, ISP or equivalent); specific tool experience is valuable but not mandatory.

  • Experience generating and validating IO connectivity deliverables (pad ring DEF, IO netlist, bump assignment) for physical design hand-off).

  • Understanding of Foundation and Hard IP related views including RTL, lef and liberty

  • Working proficiency in flow automation and scripting using tcl and/or python

  • Excellent analytical, communication (written and verbal), and documentation skills.

Preferred qualifications:

  • M.S degree in electrical engineering

  • Basic understanding of DFT methodologies mainly JTAG/Boundary Scan (IEEE 1149.1) architecture and TAP controller operation for including post-silicon bring-up and debug flows for SoC IO validation

  • Exposure to RTL compilation and Synthesis flow including understanding of Verilog/System Verilog is desirable

  • Working knowledge of Industry standard Project management, versioning and tracking tools e.g. SVN, JIRA.

Travel Time:

0% - 25%

Pay Range:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive base pay, restricted stock units, and quarterly bonus payments. In addition to these components, our package includes health benefits that begin day one, retirement savings plans, and an industry leading IESPP program with a 6-month look back feature. Find more information about all our benefits at the link below:

Benefits of working at Microchip

The annual base salary range for this position is $107,000 - $226,000.*

*Range is dependent on numerous factors including job location, skills and experience.

To all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.

Opportunity

Engineering Leadership work from LinkedIn, X, Reddit and Upwork, in one list.

Each morning you get everything that fits, strongest first.

Engineering Leadership

Find me work

By the team behind techroles.

Find me work
Opportunity

Engineering Leadership work from LinkedIn, X, Reddit and Upwork, in one list.

Each morning you get everything that fits, strongest first.

Find me work

By the team behind techroles.