Sr Principal Engineer -SIPI
At a glance
Senior Engineering Leadership role at Cadence. San Jose · full-time · $154,000–$286,000 base.
techroles summary, based on the employer's posting.
What you'll do
- Optimize and verify signal and power integrity in test-chip packages and evaluation boards
- Build extracted and measured channel models for R&D chip designers, then run link simulations with S-parameter and IBIS-AMI models
- Set package and PCB design guidance, review customer layouts and simulations, and advise on changes that support IP performance
- Troubleshoot SI/PI issues in test chips and customer ASICs in the lab
What you bring
- A master’s or doctoral degree in electrical engineering or a similar discipline
- At least three years of experience, preferably with high-speed SerDes and PHYs, plus a solid grasp of SerDes architecture
- Practical lab experience with high-speed test instruments and fluency in 3D and 2.5D extraction tools
- Experience simulating IBIS-AMI models and comparing simulation results with lab measurements
- Working knowledge of PCB and FCBGA design requirements, with strong debugging and communication skills
Who this fits
This is a hands-on technical role suited to an experienced engineer who can work across simulation, package and board design, and lab debugging. The position is based in San Jose.
From the employer
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Sr Principal Enginee
This is a unique opportunity to join the HPP IP R&D Group at Cadence Design Systems. We are looking for a Sr Principal SI/PI Engineer who will be a key contributor to our advanced high speed IP products. This is a hands-on technical position.
Main Job Tasks and Responsibilities:
• Work on test chip package design SI/PI optimization and verification.
• Work on evaluation board design optimization for best SI/PI performance.
• Provide extracted and measured channel models for chip designers in the R&D team.
• Help with package and PCB SI/PI design guidelines and customer support on SI/PI related inquiries.
• Review customer package and board designs and simulation results. Help with providing feedback to customers to ensure best possible performance of our IP in their ASIC.
• Work on link performance simulations using S-parameter channel models and IBIS-AMI behavioral models.
• Help with SI/PI related debug of test chips or customer ASICs in the lab.
Position Requirements:
• M.S. or Ph.D. Electrical Engineering (or similar degree)
• 3+ years of experience preferably working with high speed SerDes and PHYs
• Good understanding of high speed SerDes architecture
• Hands on lab experience with instruments like high speed oscilloscopes, TDRs, VNAs, spectrum analyzers, etc.
• Fluent with using 3D and 2.5D extraction tools like Sigrity Clarity/PowerSI or Ansys HFSS/SIwave
• Experience with IBIS-AMI model simulations
• Experience with simulation result to lab measurement correlation
• Good understanding of PCB and FCBGA design rules and requirements
• Strong debugging and problem-solving skills
• Excellent communication and presentation skills to effectively communicate with both customers and internal stake holders
The annual salary range for California is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.