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techroles

Senior Software Architect

Cadence Open · verified Oct 24, 2026
San Jose Full-time Senior Engineering Leadership

At a glance

Senior Engineering Leadership role at Cadence. San Jose · full-time · $210,000–$390,000 base.

SalaryStated by Cadence
$210,000 – $390,000
Base salary for this role, in USD per year, as published in the posting.
This role, from CadenceOur estimate for the market: $195,000–$243,075Median $221,516
The range includes the market median of $221,516 for senior engineering leadership roles in San Jose.
Worked out from 42 postings that stated pay, median $221,516. Last updated Oct 21, 2026.
RoleEngineering Leadership
SenioritySenior
LocationSan Jose
EmploymentFull-time
Base pay$210,000–$390,000
PostedSep 24, 2026 · 4w ago
Role brief

techroles summary, based on the employer's posting.

What you'll do

  • Extend Xcelium’s RTL and logic simulator with new capabilities, then maintain features already in use
  • Build and improve Timing Constraints Verification, including graph algorithms for SDC constraints across very large graphs
  • Find performance bottlenecks and optimize C/C++ code to reduce compile time and memory use
  • Guide junior engineers, review code and specifications, and work with teammates across locations
  • Write specifications and unit tests, and contribute to technical discussions and process changes

What you bring

  • A relevant master’s degree with at least twelve years of experience, or a doctorate with at least ten years
  • At least ten years developing EDA software, with strong RTL or logic simulation, SDC constraints and timing-analysis expertise
  • Strong C/C++ skills, knowledge of SystemVerilog or Verilog, and experience with concurrent programming

Who this fits

This senior engineering role suits someone with deep EDA experience who can tackle performance work and guide junior engineers. You’ll collaborate with a geographically distributed team. The role is based in San Jose, California.

From the employer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Join the team behind Xcelium, the industry-leading logic simulator, to architect the next generation of hardware verification technology. As a Senior Engineer in the System Verification Group, you will be at the forefront of EDA innovation, evolving the Xcelium simulator to meet the staggering complexity of future AI and hyperscale chip designs. You will be part of an innovative, geographically distributed team dedicated to advancing the capabilities of RTL/logic simulation for semiconductor technology. The work environment encourages collaboration, technical excellence, and continuous learning.

We are looking for experienced C++ software engineers who thrive on "impossible" scaling challenges and want to invent the algorithms that will power tomorrow’s silicon.

Responsibilities:

  • Enhance and support Xcelium RTL/logic simulator engine to add new features and extend existing features.
  • Enhance and support Timing Constraints Verification technology used inside Xcelium simulator.
  • The role involves designing, tuning, and innovating graph algorithms involving SDC constraints support on multi‑billion‑node graphs.
  • Conduct deep-dive bottleneck analysis and implement performance optimizations in C/C++ to improve compilation speed and memory footprint.
  • Lead junior engineers and collaborate with global team members to deliver high-quality results in a distributed environment.
  • Contribute to technical discussions, code reviews, and process improvements.
  • Write Specifications and Unit Tests for your code.

Position Requirements/Qualifications:

  • MS in Computer Science or Electrical Engineering with a minimum of 12 years of experience OR PhD with a minimum of 10 years of experience
  • 10+ years of experience in EDA software development.
  • Strong background in RTL/Logic Simulation, SDC constraints and Timing Analysis especially path exceptions handling in a STA tool.
  • Excellent programming skills in C/C++ and a deep understanding of SystemVerilog or Verilog.
  • Experience in multi-threaded/ concurrent programming.
  • Ability to quickly learn new technologies and adapt to project requirements.
  • Prior experience with RTL/logic simulation software development is an added plus.

The annual salary range for California is $210,000 to $390,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We’re doing work that matters. Help us solve what others can’t.

Opportunity

Engineering Leadership work from LinkedIn, X, Reddit and Upwork, in one list.

Each morning you get everything that fits, strongest first.

Engineering Leadership$210k+

Find me work

By the team behind techroles.

Find me work
Opportunity

Engineering Leadership work from LinkedIn, X, Reddit and Upwork, in one list.

Each morning you get everything that fits, strongest first.

Find me work

By the team behind techroles.