Principal EDA Software Engineer (C++, Characterization)
Cadence Open · verified Oct 24, 2026 At a glance
Senior Software Engineering role at Cadence. San Jose · full-time · $136,500–$253,500 base.
techroles summary, based on the employer's posting.
What you'll do
- Extend the current tool architecture so it can support timing analysis
- Build analysis frameworks for effects that dominate at n5 and smaller process nodes
- Apply machine learning to improve the speed, capacity and usability of existing solutions
What you bring
- At least eight years developing EDA tools, with expertise in one or more listed transistor-level analysis areas
- Strong C++ skills, including experience building and maintaining applications on Unix or Linux
- You can design data structures and algorithms, apply software engineering practices, and read transistor- or gate-level schematics
- Experience with software quality and development processes
Who this fits
This senior engineering role suits someone focused on C++ development for EDA tools and transistor-level analysis. The position is based in San Jose.
From the employer
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Join our expert R&D team as we create technologies and products that enable static and dynamic transistor-level analysis of the most advanced custom digital and mixed-signal circuits, powering the communication, IoT, and AI markets.
Key Responsibilities
- Enhance and expand existing tools' architecture to cover timing analysis.
- Create new frameworks for analyzing effects dominant at n5 and below.
- Leverage machine learning technology to achieve significant improvements in speed, capacity, and usability over existing solutions.
Must-Have Qualifications
- 8+ years of experience in development of EDA tools and expertise in one or more areas: transistor-level timing, power, noise, aging, reliability, and EMIR analysis.
- Hardcore C++ knowledge, particularly in a Linux environment.
- Strong proficiency in designing data structures, algorithms, and applying software engineering principles.
- Industry experience developing and maintaining C++ based applications on Unix or Linux platforms.
Requirements
- Experience with quality and software processes.
- Proficiency in designing data structures, algorithms, and software engineering principles.
- Ability to analyze transistor or gate-level schematics.
- BS degree in Computer Science, Electrical Engineering, or Computer Engineering preferred.
Nice-to-Have Skills
- Experience in development of circuit simulation or library characterization programs.
- Understanding of SPICE simulation transistor models at a high level.
- Experience with distributed programming, database design, and cloud APIs for distributed computing.
Why Cadence?
At Cadence, you’ll work alongside industry leaders and innovators who are passionate about advancing technology. Your contributions will directly impact the development of cutting-edge tools and solutions for the communication, IoT, and AI industries. We foster a collaborative environment where your expertise and ideas will shape the technology of tomorrow.
Apply Today
If you are ready to make a difference and push the boundaries of EDA technology, we encourage you to apply and join Cadence’s world-class R&D team.
The annual salary range for California is $136,500 to $253,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
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